Low‐power and area efficient binary coded decimal adder design using a look up table‐based field programmable gate array

Published in IET Circuits, Devices and Systems, 2016

Recommended citation: Sworna, Z. T., UlHaque, M., Tara, N., Hasan Babu, H. M., & Biswas, A. K. (2016). Low‐power and area efficient binary coded decimal adder design using a look up table‐based field programmable gate array. IET Circuits, Devices & Systems, 10(3), 163-172. https://ietresearch.onlinelibrary.wiley.com/doi/full/10.1049/iet-cds.2015.0213