An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem

Published in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017

Recommended citation: Sworna, Z. T., Haque, M. U., Babu, H. M. H., Jamal, L., & Biswas, A. K. (2017, July). An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem. In 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (pp. 116-121). IEEE. https://ieeexplore.ieee.org/abstract/document/7987505